High performance IC chips commonly referred to simply as chips, present three concomitant problems, namely, the requirement to connect many signals paths, the delivery of electric power to the chip and the removal of heat from the chip. State of the art chips may only be in the order of 14 millimeters on a side and yet require as many as 500 or more electrical connections in order to receive the necessary power and reference voltages to operate the chip and to distribute the various electrical signals to and from the chip. One common technique for making all of the necessary connections to such a chip is to mount the chip on a flexible lead frame. The lead frame is essentially a flexible circuit or tape having a multiplicity of printed conductors or runs extending from contacts spaced around the periphery of the chip to terminals distributed around the periphery of the lead frame. With the chip being connected thusly to the lead frame, the latter can be connected to a printed wiring board or other interconnect substrate by soldering the lead frame terminals to correspondingly positioned contacts on the substrate.
A chip assembly of this type which also incorporates a heat sink to remove heat from the chip is disclosed in pending U.S. Pat. application Ser. No. 162,671, filed Mar. 1, 1988, entitled METHOD AND APPARATUS FOR PACKAGING AND COOLING INTEGRATED CIRCUIT CHIPS, which application is assigned to the owner of this application. The so-called TAB or chip-on-tape assembly disclosed in that application can remove heat from the chip and provide a large number of leads for signals, and power and reference voltages. However, the concentration of supply current contact points around the chip perimeter and the associated clustered conductor runs on the lead frame constitute relatively high inductance power connections between the chip and the substrate. This high inductance may sometimes adversely affect the stability of on-chip reference supplies that are subjected to very fast transient current disturbances. Such disturbances can arise, for example, due to simultaneously switching drivers. Current state-of-the art CMOS and ECL chips should be able to handle switching transients in the order of 25 amp/ns without adverse effects on electrical performance. But, the known chip assemblies achieve this level of performance only with difficulty. The delivery of power to the peripheral contacts of a TAB-type chip assembly may also result in a relatively high IR drop of the steadystate (DC) components of the chip and the chip can sometimes suffer electromigration failure in the on-chip power distribution due to excessively high peak current densities.